As semiconductor technology has advanced, the amount and speed of logic available on an integrated circuit (IC) has increased more rapidly than the number and performance of input/output (I/O) connections. As a result, IC die stacking techniques have received renewed interest to address the interconnection bottleneck of high-performance systems. In stacked IC applications, two or more ICs are stacked vertically and interconnections between them are made by wire bonding at chip periphery or by forming high aspect ratio through die vias (TDVs). There are several approaches for stacking ICs. Multiple silicon device layers can be grown epitaxially or fully processed ICs can be bonded for vertical integration.
In addition, the need to integrate more functionality on each IC die has lead to the development of more and more mixed signal ICs (i.e., ICs having digital and analog circuits). For example, mixed signal ICs may include a large digital circuit and one or more smaller mixed signal circuits and/or analog circuits, such as analog-to-digital (ND) converters, phase locked loops (PLLs), delay locked loops (DLLs), voltage controlled oscillators (VCOs), and the like. In a mixed signal IC, however, attention must be paid to the interaction between the digital and analog circuits. The digital circuits will create noise, particularly from switching actions, which will degrade the performance of analog circuits if such noise is not compensated. A major part of this noise coupling occurs via the common substrate.
In particular, digital circuits generate significant amounts of undesired noise currents both in the substrate and on the power supply lines during operation. Since the underlying substrate is semi-conductive by nature, the noise generated by digital circuits can easily be injected into the substrate and propagate through the die. This substrate noise may be injected into sensitive circuits, such as analog and/or mixed signal circuits on the die and affect their operation. Substrate noise generation is caused by various mechanisms, including impact ionization, capacitive coupling, and power supply-ground bounce. Notably, capacitive coupling of noise into the substrate is caused by displacement currents in the substrate created by switching signals. Capacitive coupling is attributed to multiple parasitic capacitances, including reverse-biased source/drain to bulk junction capacitance, n-well to bulk capacitance, interconnect-to-substrate capacitance, and the like.
In a conventional IC die, capacitively-coupled noise propagates laterally and vertically through the substrate, but overall is confined near the active surface of the substrate. Presently, capacitively-coupled noise in the substrate is minimized by following appropriate design rules to maintain a safe distance between a noisy circuit and a noise-sensitive circuit. As the active area on a die is at a premium, it is not always desirable or even possible maintain such safe distances in a design. Furthermore, unlike substrate coupling in conventional ICs, substrate coupling in stacked ICs with TDVs occurs deep into the substrate. This is due to the capacitive-coupling of noise from signal TDVs that extend through the substrate. Accordingly, there exists a need in the art for techniques to reduce substrate-coupling of noise from TDVs in stacked ICs.